This is a project I’ve been working on for the Clay-Wolkin Research Fellowship at HMC. It’s a visualizer for specially-formatted Verilog files which have position information for cells. It also visualizes delay (and, in the future, energy) information output from the Stanford Circuit Optimization Tool (SCOT; manual). A sample output file of an 8×8 array multiplier is shown below:
It’s not a terribly-useful tool unless you’re doing exactly what we’re doing, but I guess it’s kind of cool. Anyhow, git repo is public, woo:
git clone http://files.roguelazer.com/projects/cwviz.git
As usual, let me know if you have any questions or comments.